avalanche rugged technology rugged gate oxide technology lower input capacitance improved gate charge extended safe operating area lower leakage current : 10 m a (max.) @ v ds = -200v low r ds(on) : 2.084 w (typ.) advanced power mosfet thermal resistance junction-to-case junction-to-ambient junction-to-ambient r q jc r q ja r q ja o c/w characteristic max. units symbol typ. features d 2 -pak 1. gate 2. drain 3. source 1 3 2 1 2 3 i 2 -pak * * when mounted on the minimum pad size recommended (pcb mount). absolute maximum ratings drain-to-source voltage continuous drain current (t c =25 o c) continuous drain current (t c =100 o c) drain current-pulsed gate-to-source voltage single pulsed avalanche energy avalanche current repetitive avalanche energy peak diode recovery dv/dt total power dissipation (t a =25 o c) total power dissipation (t c =25 o c) linear derating factor operating junction and storage temperature range maximum lead temp. for soldering purposes, from case for 5-seconds characteristic value units symbol i dm v gs e as i ar e ar dv/dt p d i d t j , t stg t l a v mj a mj v/ns w w w/ o c a o c v dss v * o 1 o 2 o 1 o 1 o 3 1/8 ? sfw/i9610 bv dss = -200 v r ds(on) = 3.0 i d = -1.75 a -200 -1.75 -1.0 -7.0 30 143 -1.75 2.0 -5.0 3.1 20 0.16 - 55 to +150 300 6.25 40 62.5 -- -- -- w + _ ?1999 fairchild semiconductor corporation rev. b
p-channel power mosfet electrical characteristics (t c =25 o c unless otherwise specified) drain-source breakdown voltage breakdown voltage temp. coeff. gate threshold voltage gate-source leakage , forward gate-source leakage , reverse characteristic symbol max. units typ. min. test condition static drain-source on-state resistance forward transconductance input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time total gate charge gate-source charge gate-drain( ? miller ? ) charge g fs c iss c oss c rss t d(on) t r t d(off) t f q g q gs q gd bv dss d bv/ d t j v gs(th) r ds(on) i gss i dss v v/ o c v na m a w w pf ns nc -- -- -- -- -- -- -- -- -- -- -- -- -- v gs =0v,i d =-250 m a i d =-250 m a see fig 7 v ds =-5v,i d =-250 m a v gs =-30v v gs =30v v ds =-200v v ds =-160v,t c =125 o c v gs =-10v,i d =-0.9a v ds =-40v,i d =-0.9a v dd =-100v,i d =-1.75a, r g =18 see fig 13 v ds =-160v,v gs =-10v, i d =-1.75a see fig 6 & fig 12 drain-to-source leakage current v gs =0v,v ds =-25v,f =1mhz see fig 5 source-drain diode ratings and characteristics continuous source current pulsed-source current diode forward voltage reverse recovery time reverse recovery charge i s i sm v sd t rr q rr characteristic symbol max. units typ. min. test condition -- -- -- -- -- a v ns m c integral reverse pn-diode in the mosfet t j =25 o c,i s =-1.75a,v gs =0v t j =25 o c,i f =-1.75a di f /dt=100a/ m s o 4 o 4 o 4 o 4 o 5 o 5 w o 4 o 1 o 4 sfw/i9610 -200 -- -2.0 -- -- -- -- -- -0.2 -- -- -- -- -- 45 16 10 20 27 12 9 1.8 4.8 -- -- -4.0 -100 100 -10 -100 3.0 -- 285 65 25 30 50 65 35 11 -- -- 1.1 220 -- -- -- 110 0.42 -1.75 -7.0 -4.0 -- -- notes ; repetitive rating : pulse width limited by maximum junction temperature l=70mh, i as =-1.75a, v dd =-50v, r g =27 w * , starting t j =25 o c i sd -1.75a, di/dt 250a/ m s, v dd bv dss , starting t j =25 o c pulse test : pulse width = 250 m s, duty cycle 2% essentially independent of operating temperature < _ < _ < _ < _ o 1 o 2 o 3 o 4 o 5
p-channel power mosfet fig 1. output characteristics fig 2. transfer characteristics fig 6. gate charge vs. gate-source voltage fig 5. capacitance vs. drain-source voltage fig 4. source-drain diode forward voltage fig 3. on-resistance vs. drain current sfw/i9610 10 -1 10 0 10 1 10 -1 10 0 @ notes : 1. 250 m s pulse test 2. t c = 25 o c v gs top : - 15 v - 10 v - 8.0 v - 7.0 v - 6.0 v - 5.5 v - 5.0 v bottom : - 4.5 v -i d , drain current [a] -v ds , drain-source voltage [v] 2 4 6 8 10 10 -1 10 0 25 o c 150 o c - 55 o c @ notes : 1. v gs = 0 v 2. v ds = -40 v 3. 250 m s pulse test -i d , drain current [a] -v gs , gate-source voltage [v] 0 1 2 3 4 5 6 7 0 2 4 6 8 10 @ note : t j = 25 o c v gs = -20 v v gs = -10 v r ds(on) , [ w ] drain-source on-resistance -i d , drain current [a] 0.5 1.0 1.5 2.0 2.5 3.0 10 -1 10 0 150 o c 25 o c @ notes : 1. v gs = 0 v 2. 250 m s pulse test -i dr , reverse drain current [a] -v sd , source-drain voltage [v] 0 2 4 6 8 10 0 5 10 v ds = -160 v v ds = -100 v v ds = -40 v @ notes : i d =-1.75 a -v gs , gate-source voltage [v] q g , total gate charge [nc] 10 0 10 1 0 100 200 300 400 c iss = c gs + c gd ( c ds = shorted ) c oss = c ds + c gd c rss = c gd @ notes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] -v ds , drain-source voltage [v]
p-channel power mosfet fig 7. breakdown voltage vs. temperature fig 8. on-resistance vs. temperature fig 11. thermal response fig 10. max. drain current vs. case temperature fig 9. max. safe operating area p dm . t 1. t 2. sfw/i9610 -75 -50 -25 0 25 50 75 100 125 150 175 0.0 0.5 1.0 1.5 2.0 2.5 3.0 @ notes : 1. v gs = -10 v 2. i d = -0.9 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] 10 0 10 1 10 2 10 -2 10 -1 10 0 10 1 10 ms dc 1 ms 0.1 ms @ notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse operation in this area is limited by r ds(on) -i d , drain current [a] -v ds , drain-source voltage [v] -75 -50 -25 0 25 50 75 100 125 150 175 0.8 0.9 1.0 1.1 1.2 @ notes : 1. v gs = 0 v 2. i d = -250 m a -bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 -i d , drain current [a] t c , case temperature [ o c] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -1 10 0 single pulse 0.2 0.1 0.01 0.02 0.05 d=0.5 @ notes : 1. z q jc (t)=6.25 o c/w max. 2. duty factor, d=t 1 /t 2 3. t jm -t c =p dm *z q jc (t) z q jc (t) , thermal response t 1 , square wave pulse duration [sec]
p-channel power mosfet fig 12. gate charge test circuit & waveform fig 13. resistive switching test circuit & waveforms fig 14. unclamped inductive switching test circuit & waveforms e as = l l i as 2 ---- 2 1 -------------------- bv dss -- v dd bv dss v in v out 10% 90% t d(on) t r t on t off t d(off) t f charge v gs -10v q g q gs q gd vary t p to obtain required peak i d -10v v dd c l l v ds i d r g t p dut bv dss t p v dd i as v ds (t) i d (t) time v dd ( 0.5 rated v ds ) -10v v out v in r l dut r g -3ma v gs current sampling (i g ) resistor current sampling (i d ) resistor dut v ds 300nf 50k w 200nf 12v same type as dut ? current regulator ? r 1 r 2 sfw/i9610
p-channel power mosfet fig 15. peak diode recovery dv/dt test circuit & waveforms dut v ds + -- l i s driver v gs r g compliment of dut (n-channel) v gs ? dv/dt controlled by ?r g ? ? i s controlled by duty factor ?d? v dd 10v v gs ( driver ) i s ( dut ) v ds ( dut ) v dd body diode forward voltage drop v f i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- sfw/i9610
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